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ma17501 1/35 the ma17501 execution unit is a component of the dynex semiconductor mas281 chip set. other chips in the set include the ma17502 control unit and the ma17503 lnterrupt unit. also available is the peripheral ma31751 memory management unit/block protection unit. these chips in conjunction implement the full mll-std-1750a lnstruction set. the ma17501 - consisting of a full function 16-bit alu, 24 x 16-bit dual-port ram register file, 32-bit barrel shifter, 4 x 24- bit parallel multiplier, synchronisation clock generation logic, and microcode decode logic - provides all computational, logical, and synchronisation functions for the chip set. table 1 provides brief signal definitions. the ma17501 is offered in several package styles including; dual-in-line, flatpack and leadless chip carrier. full packaging information is given at the end of the document. features n mil-std-1750a instruction set architecture n full performance over military temperature range (-55 c to +125 c) n radiation hard cmos/sos technology n 16-bit bidirectional address/data bus n 16-bit full function registered alu n 32-bit barrel shifter n 24 x 16-bit dual-port ram file ? 16 user accessible general purpose registers ? 8 microcode accessible registers n 4 x 24-bit parallel multiplier ? 48-bit accumulator ? 16-bit x 16-bit multiply in 4 machine cycles n instruction pre-fetch n mas281 integrated built-in self test n ttl compatible system interface block diagram 1.0 system considerations the ma17501 execution unit (eu) is a component of the dynex semiconductor mas281 chip set. this chip set implements the full mll-std-1750a instruction set architecture. the other chips in the set are the ma17502 control unit (cu) and the ma17503 interrupt unit (iu). also available is the peripheral ma31751 memory management unit/block protection unit (mmu(bpu)). figure 1 depicts the relationship between the chip set components. the eu provides the arithmetic and logical computation resources for the chip set. the eu also provides program sequencing logic in support of branching and subroutine functions. the lu provides interrupt and fault handling resources, dma interface control signals, and the three mil-std-1750a timers. the eu and lu are each controlled by microcode from the cu. the mmu(bpu) may be configured to provide 1m-word memory management (mmu) and/or 1k-word memory block write protection (bpu) functions. ma17501 radiation hard mil-std-1750a execution unit replaces march 1997 version, ds4548 - 2.3 ds4548 - 3.2 january 2000
ma17501 2/35 figure 1: mas281 chip set with optional ma17504 and support rams as shown in figure 1, the mas281 is the minimum processor configuration consisting of an execution unit, a control unit, and an interrupt unit. this configuration is capable of accessing a 64k-word address space. addition of a ma31751 allows access to a 1m-word address space and/or provides hardware support for 1k-word memory block write protection. the eu, as with all components of the mas281 chip set, is fabricated with gec plessey semiconductors cmos/sos process technology. lnput and output buffers associated with signals external to the mas281 are ttl compatible. detailed descriptions of the eu's companion chips are provided in separate data sheets. additional discussions on chip set system considerations, interconnection details, and dals mix benchmarking analysis are provided in separate applications notes. the execution unit consists of a full function 16-bit alu, 32-bit barrel shifter, 4 x 24-bit parallel multiplier, 24 x 16bit dual-port ram register file, processor status word register, three operand transfer registers, three instruction fetch registers, various interconnect buses, synchronization clock generation logic, and microcode decode logic. details of these components are depicted in figure 2 and are discussed below: 2.0 architecture 2.1 alu the alu is a full function 16-bit arithmetic/logic unit capable of performing arithmetic and logic operations on either one or two 16-bit operands in a single machine cycle. ln addition to operand manipulation, the alu is used to compute memory addresses. the alu supports 16-bit fixed-point single-precision, 32-bit fixed-point double-precision, 32-bit floating-point, and 48-bit floating-point extended-precision data in twos complement representation. double-precision and extended-precision operands are passed through the alu 16 bits at a time on consecutive machine cycles. machine flags provide an indication of alu results and are used to set condition status (cs) bits c, p, z, and n in the status word register. condition status bits and the status word register are discussed below.
ma17501 3/35 table 1: signal definitions signal i/o definition ad00 - ad15 i/o external 16-bit address/data bus as o/z address strobe indicates address lnformation on a/d bus clkpc o precharge clock clk02 o phase 2 clock pause l dma acknowledge (a/d bus to be used for dma) ds o/z data strobe lndicates data lnformation on a/d bus hldak o hold acknowledge hold l hold request suspends lnternal processor functions ln/ op o/z lnstruction/operand lndicates type of memory access intre o lnterrupt enable lrdy l lnterrupt unit ready signal m/ lo o/z memory or lnput/output lndicates transaction on a/d bus m00 - m19 l 20-bit microcode bus osc l external oscillator clock ovl o overflow lndicator plf l privileged instruction fault rd /w o/z read/write indicatesdata direction on a/d bus rdy l ready lnforms cpu of the conclusion of external bus cycle reset l reset indicates device initialization synclk o interrupt unit's sync clock sync o system clock - cpu sync clock (external) sysclk1 o system clock (internal) test i test enable t1 o branch or jump control vdd power (external), 5 volts gnd ground 2.2 barrel shifter the barrel shifter is a 32-bit input, 16-bit output right shift network. a 32-bit operand may be shifted right arithmetically, logically, or cyclically up to 31 bit positions in a single machine cycle. while not directly accessible or visible to user programs, the barrel shifter is utilized by microcode to effect all shift, rotate, and normalize instructions with minimum execution time. 2.3 parallel multiplier the parallel multiplier performs a 4-bit multiplier by 24-bit multiplicand multiplication plus accumulation in a single machine cycle. only four machine cycles are required to complete a 16-bit by 16-bit multiplication. contained within the multiplier is a 48-bit product accumulation register with the lower 24 bits serving as a source operand register. on each multiply machine cycle, the lower four bits of the accumulator are multiplied by 24 bits from the two alu operand source buses (r and s). the lower 24 bits of this 28- bit product are then added to the upper 24 bits of the accumulator and the whole accumulator is shifted right four bits. this right shift makes room for the upper four bits of the product. the four bits shifted out are used in the next multiply iteration. 2.4 dual-port register file the register file is a dual port ram structure containing 24, 16-bit registers. sixteen of these registers are general purpose and user accessible. these user accessible registers - referred to as r0 through r15 - may be used as accumulators, index registers, base registers temporary operand registers, or stack pointers. the remaining eight registers are only accessible by microcode. adjacent registers are concatenated to effectively form 32- bit and 48-bit registers for storage of double precision and extended-precision operands, respectively. instructions access these operands by specifying the register containing the most significant part of the operand, and the register set wraps around automatically under microcode control, e.g., r15 concatenates with r0 for 32-bit operands and r15 concatenates with r0 and r1 for 48-bit operands.
ma17501 4/35 2.5 status word register the status word register (sw) holds the condition status (cs) bits c, p, z, and n generated by alu operations. the sw also stores the address state (as) and processor state (ps) fields. figure 3 defines the status word register storage format. the cs bits are stored with each logical, shift, and arithmetic operation performed by the alu as required by mll- std-1750a and remain valid until changed by subsequent operations. the cs bits are interrogated during "jump on condition" and "instruction counter relative" mll-std-1750a branch instructions. figure 2: ma17501 execution unit architecture 2.6 operand transfer registers the address (a), data output (do), and data lnput (dl) registers are referred to as operand transfer registers. these registers serve as storage buffers between internal eu buses and the eu's externally accessible address/data (ad) bus. the do register buffers data transferred from the eu to the ad bus. the a register buffers operand addresses and xlo commands onto the ad bus. the dl register buffers data transferred from the ad bus to the eu .
ma17501 5/35 figure 3: status word format 2.7 instruction fetch registers the instruction counter (ic), instruction a (ia), and instruction b (ib) registers allow sequential instruction fetches to be performed without assistance from the alu. the lc register, which holds the 16-bit address of the next instruction to be fetched from memory, is loaded automatically by reset, jump, or branch operations. once loaded, it functions as a dedicated counter to sequence from one instruction to the next. the current ic contents may be stored in registers r0 through r15 or in memory (pushed onto a stack) to provide return linkages for subroutine calls. as part of the microcoded interrupt handling routine the lc is saved in memory via the interrupt linkage pointer. registers la and ib provide an instruction look-ahead capability. ln the case of 16-bit instructions, lb holds the instruction currently executing while la holds the next instruction to be executed. ln the case of 32-bit instructions, ib and la each hold half of the instruction. ia and dl (dl stores the immediate operands) are loaded as the instruction in la is transferred to lb for execution; if the instruction in lb uses an immediate operand, la is reloaded with the next instruction while dl maintains the immediate data. this overlapping of operations allows higher performance levels to be achieved. 2.8 buses three 16-bit wide buses (r, s, and y) interconnect the eu data storage and computational elements. the r and s buses accept operands from selected eu data storage elements and route them to inputs of selected eu computational elements. the y, or destination, bus serves to route computational results either back to eu data storage and computational elements or to the various operand transfer registers. a 16-bit multiplexed address/data (ad) bus provides a communications path between the eu, other components of the mas281 chip set, and any other devices mapped into the chip set's address space. data transfers between the ad bus and the r, s, and y buses are buffered by the operand transfer registers. a 20-bit multiplexed microcode (m) bus provides a pathway between the control unit (cu) and the execution register (e) buffered microcode decode logic on the eu chip. microcode placed on this bus by the cu controls all actions of the eu. 2.9 synchronisation clock generation logic the execution unit generates all of the synchronisation clocks required by the chip set and cpu system. the eu converts an externally supplied oscillator signal into five synchronisation signals: syncn, sysclk1n,synclkn, clkpcn, clk02n. the eu generates syncn for elements external to the chip set whereas synclkn and sysclk1n are generated for the interrupt unit and internal eu synchronisation, respectively. sysclk1n is also brought out on a pin for use by external monitoring systems. the eu generates clkpcn and clk02n for use in the control unit. the cu uses clkpcn to precharge the m bus and transmit the first microword while clk02n is used to transmit microword two. the eu also contains the wait state generation interface. failure of memory or l/o subsystems to drive rdyn low at the proper time during the dsn pulse causes the eu to hold synclkn, syncn, sysclk1n, and clkpcn in the high state; clk02n, as and dsn, in the low state; and rd/wn, in/ opn and m/ion in their current states for one or more oscillator cycles beyond the end of the normal five osc cycle machine cycle. when rdyn is asserted low, the eu allows the machine cycle to conclude at the high-to-low transition of the current oscillator cycle. this will allow all the synchronisation and control signals to resume normal operation. additionally, irdyn is used to signal completion of internal l/o command control of the lnterrupt unit (iu). the iu thus can extend the duration of the above mentioned bus signals. failure of the lu to drive lrdyn low at the proper time during the dsn low pulse causes the eu to hold synclkn, syncn, sysclk1n, and clkpcn in the high state; clk02n, as, and dsn in the low state; and ln/opn, m/lon, and rd/wn in the state for the normal five osc cycle machine cycle. when the lu asserts irdyn low, the eu allows the machine cycle to conclude at the high-to-low transition of the current oscillator cycle. this will allow all the synchronisation and control signals to resume normal operation. [note: whenever the eu is executing a machine cycle which requires irdyn to drop low for completion, the machine cycle will be a minimum of six osc cycles long. the maximum duration of this machine cycle depends on the length of time that the lu holds irdyn high.]
ma17501 6/35 3.0 interface signals all signals comply with the voltage levels of table 1. ln addition, each of these functions is provided with electrostatic discharge (esd) protection diodes. all unused inputs must be held to their inactive state via a connection to vdd or gnd. a 500-ohm pull-up at the osc input pin is recommended to damp line reflections. throughout this data sheet, active low signals are denoted by either a bar over the signal name or by following the name with an "n" suffix, e.g., holdn. referenced signals that are not found on the ma17501 are preceded by the originating chip's functional acronym in parentheses, e.g., (lu)dmarn. a description of each pin function, grouped according to functional interface, follows. the function acronym is presented first, followed by its definition, its type, and its detailed description. function type is either input, output, high impedance (hi-z), or a combination thereof. timing characteristics of each of the functions described is provided in section 5.0. 3.1 power interface the power interface consists of one 5v vdd connection and three common gnd pins. 3.2 clocks the execution unit provides the synchronisation clocks for the mas281 chip set. together these clocks form the basic operation cycle. 3.2.1 oscillator (osc) lnput. the ma17501 requires a single external oscillator input for operation. the eu converts the oscillator into the five other clocks listed in this section. to minimise skew between osc edges and signals derived from osc, the osc rise and fall times should be minimised. lt is recommended that a clock driver with high drive capability, such as a 54as244, 54als244 or 54hst240, be used to drive the osc input. ln order to avoid double clocking due to line reflections, a 500-ohm pull-up resistor, placed close to the eu, is recommended. 3.2.2 synchronisation clock (syncn) output. the ma17501 provides the mas281 synchronisation clock output to synchronise external circuitry to the mas281 machine cycle. the high-to-low transition of this signal indicates the start of a new machine cycle. syncn cycles associated with external memory or l/o bus transactions are a minimum of five osc cycles in duration and may be extended by inserting wait states via the rdyn input. syncn low indicates that either an address or xlo command is on the ad bus; a high indicates data is on the bus. wait states extend the high state of syncn. syncn cycles associated with internal cpu operations are either five or six osc cycles in duration. six osc cycles are required for machine cycles associated with microcode branches or with the execution of internally (interrupt unit) decoded xlo commands. five osc cycles are used for all other internal operations, e.g., register to register transfers, alu functions, etc. [note: for mas281s operating at high osc frequencies, the lnterrupt unit logic that creates lrdyn may cause a wait state to be inserted during execution of internal xlo commands. this would result in a syncn cycle of seven osc cycles duration. though unlikely, this condition must be taken into account in implementing a rdyn generation circuit. refer to the description of the rdyn signal for further details]. 3.2.3 iu synchronisation clock (synclkn) output. the synclkn signal is a logical equivalent of the syncn signal provided for interrupt unit synchronisation. 3.2.4 system clock (sysclk1n) output. sysclk1n is the ma17501's synchronization clock. it is the logical equivalent of syncn and synclkn with the exception that during pausen low or during hldakn low, sysclk1n is held in its low state. sysclk1n, like synclkn, has a vss to vdd logic level swing. 3.2.5 precharge clock (clkpcn) output. clkpcn is used by the ma17502 control unit (cu) to synchronize the precharging of the internal m bus and most other cu operations to the mas281 machine cycle. clkpcn cycles associated with mas281 external memory or l/o bus transactions are a minimum of five osc cycles in duration and are extended when wait states are inserted via the rdyn input. clkpcn low indicates that the internal cu m bus is being precharged to the high state; the low-to-high transition places the lower 20 bits of a microinstruction on the external m bus. wait states extend the high state of clkpcn. when pausen or hldakn is low, clkpcn is held low. clkpcn cycles associated with internal mas281 operations are either five or six osc cycles in duration. six osc cycles are required for machine cycles associated with microcode branches or with the execution of internally (lnterrupt unit) decoded xlo commands. five osc cycles are used for all other internal operations, e.g., register to register transfers, alu functions, etc. [note: for mas281s operating at high osc frequencies, the lnterrupt unit logic that creates lrdyn may cause a wait state to be inserted during execution of internal xlo commands. this would result in a clkpcn cycle of seven osc cycles duration.]
ma17501 7/35 3.2.6 phase 2 clock (clk02n) output. clk02n is used by the ma17502 control unit (cu) in conjunction with clkpcn to synchronize microinstruction transmission on the m bus to the mas281 machine cycle. clk02n cycles associated with mas281 external memory or l/o bus transactions are a minimum of five osc cycles in duration and are extended when wait states are inserted via the rdyn input. the high-to-low transition of clk02n places the upper 20 bits of a microinstruction on the external m bus. wait states extend the trailing (based on syncn high-to- low beginning the machine cycle) low state of clk02n. when pausen or hldakn is low, clk02n is held high. clk02n cycles associated with internal mas281 operations are either five or six osc cycles in duration. six osc cycles are required for machine cycles associated with microcode branches or with the execution of internally (interrupt unit) decoded xlo commands. five osc cycles are used for all other internal operations, e.g., register to register transfers, alu functions, etc. [note: for mas281s operating at high osc frequencies, the interrupt unit logic that creates irdyn may cause a wait state to be inserted during execution of internal xlo commands. this would result in a clk02n cycle of seven osc cycles duration.] 3.3 bus control this group of signals is provided to control address/ data (ad) bus transmissions (see figure 4). the signals indicate when address or data information is on the ad bus and what type of transaction is taking place during a particular machine cycle. 3.3.1 address strobe (as) output/hi-z. as high indicates that the address/data (ad) bus contains address information. the address information is assured stable at the high-to-low transition of this signal. ln this way, as provides the necessary control for a system address bus transparent latch system interface. the interrupt unit uses as to extract the xlo command information off the ad bus for internally decoded xlo commands, and the memory management unit/block protection unit (mmu(bpu)) uses as to extract address information for memory management and block protection functions, and to extract xlo command information for mmu(bpu) decoded xlo commands. as is placed in the high-impedance state during dma cycles by pausen low and during the hold state by hldakn low. during internal non-ad bus related cpu operations, as is held low for the entire machine cycle via microcode control. figure 4: typical mas281/ma17504 system interface
ma17501 8/35 3.3.5 instruction/operand (in/opn) output/hi-z. ln/opn high indicates an instruction is to be read from memory during the current ad bus cycle. in/opn is low for all other mas281 directed ad bus transfers. the memory management unit/block protection unit (mmu(bpu)), when configured as a mmu, uses ln/opn to select the proper page register set within the specified page register group. in/opn is asserted at the syncn high-to-low transition and remains valid for the duration of the current syncn period. ln/opn is placed in the high-impedance state during dma cycles by pausen low and during the hold state by hldakn low. 3.3.6 ready (rdyn) input. during external ad bus transfers (those dealing with devices external to the mas281 chip set), a low is required on this input to allow the mas281 machine cycle to complete (high-to-low transition of syncn). rdyn high is used to prolong the data portion of the machine cycle (syncn high) to accommodate slow memory and l/o devices. the mas281 assumes memory or l/o devices are not ready to provide (accept) data to (from) the ad bus, and requires these devices to signal their readiness via the rdyn input. a low on rdyn, enveloping the current machine cycle's fifth (or later) osc cycle high-to-low transition, allows the current machine cycle to complete (syncn high-to-low transition) at the following low-to-high transition of the osc input. 3.3.2 data strobe (dsn) output/hi-z. dsn low indicates that data is on the ad bus (write/output cycles) or that the mas281 ad bus drivers are in the high-impedance state (read/input cycles). for write/output cycles, the data is guaranteed stable at the low-to-high transition of dsn. for read/input cycles, the dsn low-to-high transition indicates the acceptance of data by the mas281 (sysclk1n high-to-low transition latches ad bus data into the la and dl registers). dsn is placed in the high-impedance state during dma cycles by pausen low and during the hold state by hldakn low. dsn is held high, for the entire machine cycle, during internal non-ad bus operations via microcode. 3.3.3 read/write (rd/wn) output/hi-z. rd/wn defines the direction of data flow on the bidirectional ad bus and provides read/write cycle information to the mmu(bpu) for write protection control. rd/wn high indicates a read/input bus cycle and data transfer to the mas281. rd/wn low indicates a write/output bus cycle and data transfer from the mas281. this signal is asserted at the syncn high-to-low transition and remains valid for the duration of the current syncn period. rd/wn is placed in the high impedance state during dma cycles by pausen low and during the hold state by hldakn low. 3.3.4 memory/lnput-output (m/ion) output/hi-z. m/lon defines the type of device involved in the data transfer occurring on the ad bus and provides functional control for the lnterrupt unit (lu) and the memory management unit/block protection unit (mmu(bpu)). the lu ignores memory transfer ad bus activity and the mmu(bpu) uses m/lon to decide whether to decode the address information on the ad bus as an mmu(bpu) xlo command or a memory address. m/lon high indicates a memory access, and m/lon low indicates an input-output operation. this signal is asserted at the syncn high-to-low transition and remains valid for the duration of the current syncn period. m/lon is placed in the high impedance state during dma cycles by pausen low and during the hold state by hldakn low. m/lon is raised high, for the entire machine cycle, during internal non ad bus operations via microcode. 3.4 buses the following is a discussion of the communication buses connecting the ma17501 to the other chips of the mas281 set. the ad bus transfers all data and instructions and the m bus provides the microcode instructions from the ma17502. 3.4.1 address/data bus (ad bus) input/output/hi-z. these signals comprise a 16-bit bidirectional multiplexed address and data bus. during external bus transfers, the ad bus accommodates the transfer of address and data information between the ma17501 and memory, or l/o ports. during internal bus operations, the ad bus provides additional communication among the execution, control, interrupt and memory management/block protection units. ad00 is the most significant bit position and ad15 is the least significant bit position of both the 16-bit data and 16-bit address. a high on this bus corresponds to a logic one and a low corresponds to a logic zero. address information is valid on the bus at the as high to- low transition. the rd/wn signal indicates the ma17501 ad bus drivers state during the data portion of the bus cycle (dsn low) and the m/lon function defines the type of device the transfer is with. the ad bus drivers are placed in the high impedance state during read operations (dsn low), during dma cycles by pausen low, and during the hold state by hldakn low.
ma17501 9/35 3.5.1 processor pause (pausen) lnput. pausen is driven low by the lnterrupt unit upon acknowledgement of a dma transfer request. a low on pausen causes the eu to place all the bus control signals (as, dsn, m/lon, rd/wn, in/opn) and the ad bus in the high impedance state, and to disable all clock outputs, except for synclkn and syncn. the requesting device maintains control of the ad bus and bus control lines until (lu)dmarn is raised high, thus causing pausen to raise high. lt is recommended that the mas281 chip set be buffered to the memory/input-output system. lf an mmu(bpu) peripheral chip is used for memory expansion/protection it must reside on the mas281 side of these buffer transceivers (see figure 4). thus, for a dma device to access the mmu(bpu), the mas281 ad bus and bus control signal drivers must be in the high impedance state to allow the dma device to drive these signals. the interrupt unit also provides the cdn signal for the directional control of the bus control transceivers. 3.5.2 processor hold request (holdn) lnput. a low on this input suspends all chip set functions (except syncn and synclkn) at the end of the current mll- std-1750a instruction. the ad bus and bus control functions (as, dsn, m/ion, ln/opn, rd/wn) are placed in the high impedance state permitting a monitor system to take control of the memory/input-output system. the internal synchronisation clocks are placed in an inactive state, which halts further instruction sequencing until holdn is released. as with dma cycles, the reason for this is to allow access to the mmu(bpu) if an expanded memory system is used. the (lu)cdn output is provided for control bus transceiver directional control during the hold state. this input should be synchronised to as falling. 3.4.2 microcontrol bus (m bus) input. the m bus is a 20-bit multiplexed microcontrol bus which provides microcoded control to the eu. the control unit multiplexes the 40-bit microcode instructions into two 20-bit words. the upper 20 bits are placed on the m bus by the clkpcn low-to-high transition and the lower 20 bits are placed on the m bus by the trailing high-to-low transition of clk02n. the microinstruction is reassembled in the eus execution (e) register and used to control eu functions during the next machine cycle. m19 is the most significant bit position and m00 is the least significant bit position for both microwords. the high order 20 bits are transmitted first, followed by the low order 20 bits of the microinstruction. a high on this bus corresponds to a logic one and low corresponds to a logic zero. 3.5 system support interface the system support interface signals have control over functions that affect the chip set as a whole. 3.5.3 processor hold acknowledge (hldakn) output. hldakn drops low after reaching the end of the mil-std-1750a instruction during which holdn was pulled low, or after encountering a bpt software instruction. the hold state is terminated by raising holdn high (if holdn low initiated the hold state), or by pulsing holdn low (if the hold state was initiated by a bpt instruction). during the hold state, software execution is suspended and the mas281 interface functions are placed in the high impedance state to allow a monitor system to take control of the memory/input-output system. 3.6 inter-chip control the following signals perform control functions internal to the mas281 chip set. these functions include microcode execution branching control and arithmetic error indication. 3.6.1 internal ready (irdyn) input. the irdyn signal is the means by which interrupt unit (iu) command cycles, involving the ad bus, are completed. the lu drops lrdyn low when the xlo command has been decoded and allows the six osc period machine cycle to complete. the irdyn and rdyn signals are effectively ored together to control the eu clock generation circuitry; therefore, rdyn should be high during lu decoded xlo commands. 3.6.2 interrupt unit microinstruction enable (intren) output. the execution unit controls the lnterrupt unit (lu) 3-bit microcode interface through the use of the intren signal. lntren low enables the lu microcode decoding logic. lu functions handled through microcode are; enable/disable dma interface xlo command control, set normal power-up discrete, load fault register, and read encoded 4-bit vector identifying the highest priority pending interrupt. machine cycles during lntren low are a special case of internal non-ad bus operations. these cycles are denoted by a six osc period machine cycle. 3.6.3 overflow indicator (ovin) output. ovln is an indication that a fixed-point overflow condition, as specified in mil-std-1750a, has occurred during an operation. the interrupt unit accepts this as an input to the pending interrupt register level four interrupt bit.
ma17501 10/35 3.6.4 privileged instruction fault (pifn) lnput. plfn low is an indication to the execution unit that a fault, requiring the current mll-std-1750a instruction to be aborted, has occurred. the faults that cause the instruction abort are 0, 5, and 8 which are, respectively, memory protect error ((iu)mproen low), an out-of-bounds memory/input- output address ((lu)exade low), or a bus fault timeout. ln response to pifn low, the eu maintains as low, dsn high, and forces the m/lon signal high for two machine cycles. ln addition, the eu will internally complete the current syncn cycle and resume operation. this allows the control unit to sequence to the interrupt handling routine without affecting the bus status. 3.6.5 branch or jump control (t1) output. the execution unit raises the t1 signal high to indicate a microcode conditional branch condition is true. the control unit accepts t1 and feeds it into the microcode address multiplexer where microinstruction branches are effected. 3.6.6 test microword (testn) lnput. the testn signal is used during chip test to load 40- bit microinstructions into the eu execution register. testn low loads e39 (msb) to e20, and testn high loads e19 to e00 (lsb). testn should be pulled-up to vdd in customer applications. 4.0 operating modes the following discussions detail the mas281 chip set operating modes from the perspective of the execution unit. mas281 operating modes involving the ma17501 include: (1) initialisation, (2) lnstruction execution, (3) interrupt servicing, (4) fault servicing, (5) dma support, and (6) software development support. 4.1 initialisation reset starts the chip set microcoded initialisation sequence, but also affects the execution unit circuitry directly. when reset is raised high, the hold state acknowledge signal (hldakn) is forced high thus releasing the mas281 from the hold state (if changing holdn is unable to release the hold state). reset also forces the clock generation circuitry to create a five osc period machine cycle by disabling state machine inputs that vary the machine cycle length. upon releasing reset, the eu hold state circuitry is enabled and the clock generation circuitry is allowed to function normally. holdn will not have an effect on chip set operation until the initialisation routine has completed because the microcode branch to the hold routine is disabled. the microcoded initialisation routine clears the lnstruction counter (lc), status word register (sw), and register file (r00-r15) and performs the blt. the successful completion of the blt is necessary to guarantee the register file is cleared at the end of the initialisation routine. the microcoded bit exercises all legal microinstruction bit combinations and tests all internally accessible structures of the mas281. for the execution unit this includes the full register set, alu, multiplier, barrel shifter, and macroflag logic. table 2 details the tests performed by each of the five blt subroutines. lf any part of blt fails, an error code identifying the failed subroutine is loaded into the lnterrupt unit fault register (via the ad bus), blt is aborted, and npu is left in the low state. table 2 defines the coding of the blt results. (lntren enables microcode control of the lnterrupt unit (lu) to raise npu high (if blt passes) and load bit error codes (if bit fails) into the lu fault register). the last action performed by the initialisation routine is to load the instruction pipeline. instruction fetches start at memory location zero (page zero) from the start-up rom (if implemented). whether or not bit passes, the processor will begin instruction execution at this point. [note: to complete initialisation and pass bit, interrupt and fault inputs must be high for the duration of the initialisation routine. also, the timers a and b must be clocked for blt success.]
ma17501 11/35 4.2 instruction execution instruction execution is characterised by a variety of operations composed of various types of machine cycles. the execution unit contains the clock generation circuitry that creates the different machine cycles depending on the particular operation being performed at the time. these operations include: (1) internal cpu cycles, (2) instruction fetches, (3) operand transfers, and (4) input/output transfers. instruction execution may be interrupted at the end of any individual machine cycle by the pausen (denoting dma operations) clock generation circuitry input, and at the beginning of any given mil-std-1750a instruction by an (iu)irn or holdn low input to the control unit. 4.2.1 internal cpu cycles all cpu data manipulation and housekeeping operations are performed using internal cpu cycles. internal cpu cycles are either five or six osc periods long and are characterised by as low and dsn, (iu)ddn, and m/ion high. section 5.0 provides timing characteristics for internal cpu cycles. the majority of lnternal cpu cycles are five osc period machine cycles. six osc period machine cycles occur when executing conditional jump or branch microinstructions; the eu is calculating the branch condition to determine the state of the t1 output signal. 4.2.2 instruction fetches lnstruction fetches are used to keep the instruction pipeline full. this ensures that the next instruction is ready for execution when the preceding instruction is completed. during jump and branch instruction execution the pipeline is flushed, then refilled via two consecutive instruction fetches starting at the new instruction location. the pipeline is also refilled as part of the interrupt and hold processing. bit test coverage bit fail codes (ft 13,14,15 ) cycles 1 mlcrocode sequencer 100 221 ib register control barrel shifter byte operations and flags 2 temporary registers (t0 - t7) 101 166 microcode flags multiply divide 3 interrupt unit - mk, pl, ft 111 214 enable/disable interrupts 4 status word control 110 154 user flags general registers (r0 - r15 5 timer a 111 763 timer b - bit pass/fail overhead - 26 note: bit pass is indicated by all zeros in ft bits 13, 14, and 15. table 2: mas281 bit summary lnstruction fetches are five (minimum) osc period machine cycles characterised by in/opn, m/lon, and rd/wn high. lnstruction fetches use pipeline registers la and ib, the instruction counter (lc), and the data input register (dl). assuming an empty instruction pipeline (as a result of a reset, jump or branch), the contents of lc are placed on the ad bus as an address. the returned value (the instruction) is stored in the ia register. the lc register is incremented (dedicated counter mode) and the next fetch is performed. this second returned value, which may be an instruction or an immediate operand, is stored in both the la and dl registers as the previous contents of ia advance to the ib register to be decoded into their microcoded routine. if the second returned value is an immediate operand, a third instruction fetch will occur with the instruction being loaded into la only; dl retains the immediate operand. the data portion (syncn high) of instruction fetch cycles can be extended beyond their minimum five osc periods by use of the rdyn signal. rdyn held high during the high-to- low transition of the machine cycles fifth osc cycle will extend the data portion of the machine cycle. the machine cycle can be completed at any succeeding osc cycle high-to-low transition by enveloping this osc edge with rdyn low. 4.2.3 operand transfers operand transfers are used to obtain operands to be used by an instruction and to save any results of an instructions execution. machine cycles associated with operand transfers are a minimum of five osc periods in duration. the rdyn signal can be used to insert wait states into the data portion of the machine cycle (syncn high) to accommodate slow memory.
ma17501 12/35 operand transfers use the address register (a), data input register (dl), and data output register (do). before the operand transfer begins, the execution unit calculates the effective operand address and stores this value in a. for write transfers the eu loads the operand into do. for operand ready cycles the eu latches the operand from the ad bus into dl at the sysclk1n high-to-low transition. all operand transfers between the mas281 and memory are referenced to the as and dsn bus control signals and are characterised by ln/opn low, m/lon and cdn high, and rd/ wn (high, read; low, write). the eu first places the contents of a on the ad bus at the sysclk1n high-to-low transition. shortly following, as is raised high to enable the system address bus transparent latch. this address is assured valid at the high-to-low transition of as. at the sysclk1n low-to high transition, dsn drops low to indicate the contents of do have been placed on the ad bus (write) or the eu ad bus drivers have been placed in the high impedance state (read). dsn subsequently raises high when the output data is stable, prior to sysclk1n dropping low, or raises high in response to sysclk1n dropping low to indicate the eu's acceptance of the input data. all operand transfer cycles are allowed to complete via the rdyn input. during the data portion of the cycle the eu assumes memory is not ready, and requires rdyn low to signal the memorys readiness to complete the cycle. if rdyn is high at the high-to-low transition of the fifth osc cycle within the operand transfer cycle, a wait state will be injected (one osc period at a time) for each osc high-to-low transition that rdyn remains high. memory readiness, thus cycle completion, is signalled by rdyn low enveloping a subsequent osc high-to-low transition. 4.2.4 input/output transfers input/output transfers are characterised by m/lon and in/ opn low, and rd/wn (high, input; low, output). as and dsn operate as during operand transfers. two different types of input/output transfers are controlled by the execution unit: internal and external. internal l/o transfers involve all xlo commands that are decoded by the lnterrupt unit (lu) and use the local ad bus to transfer response data. these commands are listed in table 3 (the only exception is rcw; it is an lu decoded, lrdyn completed, external l/o command). internal xlo commands implemented in the lu (per table 3) use a six osc period machine cycle and the irdyn cycle completion input. lnternal xlo commands implemented in the ma31751 mmu/bpu use a minimum five osc period machine cycle. the system rdyn generator provides the rdyn cycle completion input to the eu. the term "local ad bus" in this context refers to the ad bus on the processor side of the system data bus demultiplexing transceivers. the three chips of the mas281 and the ma17504 (in either configuration) reside on the local ad bus and communicate to the user system through the required address and data bus buffers, as depicted in figure 4. external i/o transfers involve all xlo and vlo instructions not included under lnternal l/o transfers. they execute during a minimum five osc period machine cycle that is extendible via rdyn, as previously described. 4.3 interrupt servicing interrupts are latched into the lnterrupt unit (lu) pending interrupt register by the synclkn high-to-low transition. the lu signals the control unit (cu) that an interrupt is pending and the cu branches to the microcoded interrupt handling routine at the completion of the currently executing mll-std- 1750a instruction. the eu supports the interrupt handling routine by enabling microcode control of the lu at the proper time via the lntren signal and by calculating the memory addresses of the service and linkage pointers based on the 4-bit interrupt priority code transmitted by the iu. machine cycles during which lntren is low are six osc periods in length. during these lntren cycles, dsn and m/lon are high, and as is low. the eu also provides a hardwired interrupt to the lu. the ovin interrupt signals a fixed-point arithmetic overflow. 4.4 fault servicing the interrupt unit (iu) latches fault inputs into the fault register on the high-to-low transition of synclkn. faults other than 0, 5, and 8 latch a level one pending interrupt in the lu and the interrupt sequencing proceeds as previously explained. faults 0, 5, and 8 caused during non-dma ad bus transactions demand more immediate attention; the mll-std-1750a instruction during which the fault occurred must be aborted. pifn indicates to the control unit that one of these faults has occurred and forces a branch to the next instruction fetch microinstruction so that the interrupt caused by the plfn fault can be serviced immediately. under normal instruction execution circumstances, the bus control signals would operate during the machine cycle between the fault and the instruction fetch machine cycle. plfn causes the bus control signals as and dsn to stay in their inactive state during this transitional machine cycle to allow the branch to the microcoded interrupt routine without performing any ad bus transactions. 4.5 direct memory access the interrupt unit dma interface logic signals the execution unit (eu) that it has acknowledged a dma request (pausen low). pausen low causes the eu to halt the synchronisation clocks clk02n (high), clkpcn (low), and sysclk1n (low); disables clock generation circuitry input that could vary the machine cycle length; and places all bus control signals and the ad bus in the high impedance state. the syncn and synclkn clocks continue to operate with a five osc cycle period. upon removal of pausen by the interrupt unit, the mas281 resumes microinstruction execution where it was interrupted. 4.6 software development support the execution unit responds to a holdn signal by suspending all internal operations upon completion of the currently executing instruction. microcode, from the control unit, directs hldakn low during the third syncn cycle after holdn has been pulled low and the previous instruction has been completed. m/lon, rd/wn, in/opn, as, dsn, and the ad bus are placed in the high impedance state permitting a monitor system to take control of the memory/input-output system. raising holdn releases the mas281 from the hold state and instruction execution begins by refilling the pipeline. the execution of a bpt instruction also causes hldakn to drop low and the bus control signals and ad bus to be placed in the high impedance state. a low pulse on holdn releases the mas281 from the bpt initiated hold state.
ma17501 13/35 cycles* command operation code(hex) mnemonic m p b implemented in mas281 set fault register 0401 sfr 2 3 9 set lnterrupt mask 2000 smk 2 3 9 clear lnterrupt request 2001 cllr 2 3 9 enable lnterrupts 2002 enbl 2 3 9 disable interrupts 2003 dsbl 2 3 9 reset pending interrupt 2004 rpi 2 3 9 set pending lnterrupt register 2005 spi 2 3 9 reset normal power up discrete 200a rns 2 3 9 write status word 200e wsw 2 3a 8.5a enable start-up rom 4004 esur 2 3 9 disable start-up rom 4005 dsur 2 3 9 direct memory access enable 4006 dmae 2 3 9 direct memory access disable 4007 dmad 2 3 9 timer a start 4008 tas 2 3 9 timer a halt 4009 tah 2 3 9 output timer a 400a ota 2 3 9 reset trigger-go 400b go 2 3 9 timer b start 400c tbs 2 3 9 timer b halt 400d tbh 2 3 9 output timer b 400e otb 2 3 9 read configuration word 8400 rcw 2 2 4 read fault register without clear 8401 rfr 2 2 4 read interrupt mask a000 rmk 2 2 4 read pending interrupt register a004 rplr 2 2 4 read status word a00e rsw 2 1 4 read and clear fault register a00f rcfr 2 2 4 lnput timer a c00a lta 2 2 4 input timer b c00e ltb 2 2 4 implemented in bpu memory protect enable 4003 mpen 2 4 8 load memory protect ram s0xx lmp 2 4 8 read memory protect ram d0xx rmp 2 3 3 implemented in mmu write instruction page register s1xy wipr 2 4 8 write operand page register 52xy wopr 2 4 8 read memory fault status a00d rmfs 2 3 3 read lnstruction page register d1xy rlpr 2 3 3 read operand page register d2xy ropr 2 3 3 m = memory, p = processor (5 osc cycles), b = processor (6 osc cycles), a = average if more than one alternative exlsts. table 3: internal i/o command summary
ma17501 14/35 5.0 timing characteristics this section provides the detailed timing specifications for the ma17501. figure 5 depicts the test loads used to obtain timing data. figures 6 through 20 depict the timing waveforms associated with various ma17501 signals. table 5 provides values for parameters specified in the timing waveforms. all timing values provided in table 5 are valid over the full military temperature range (-55 c to +125 c), and are measured from 50% point to 50% point (50% vdd supply voltage, unless otherwise specified). crosshatching in figures 6 through 20 indicates either a "dont care" or indeterminate state. load 3 load 1 load 2 figure 5: test loads
ma17501 15/35 figure 6: reset timing figure 7: basic clock timing
ma17501 16/35 figure 8: potential branch clock timing figure 9: microcode bus timing
ma17501 17/35 figure 10: internal processor cycle
ma17501 18/35 figure 11: write transfer timing
ma17501 19/35 figure 12: read transfer timing
ma17501 20/35 figure 13: internal i/o timing - write/command
ma17501 21/35 figure 14: internal i/o timing - read
ma17501 22/35 figure 15: dma access/release timing
ma17501 23/35 figure 16: hold state generation timing
ma17501 24/35 figure 17: hold state termination timing figure 18: fixed point overflow timing
ma17501 25/35 figure 19: instruction abort fault timing subgroup definition 1 static characteristics specified in table 6 at +25 c 2 static characteristics specified in table 6 at +125 c 3 static characteristics specified in table 6 at -55 c 7 functional tests at +25 c 8a functional tests at +125 c 8b functional tests at -55 c 9 switching characteristics specified in table 4b at +25 c 10 switching characteristics specified in table 4b at +125 c 11 switching characteristics specified in table 4b at -55 c table 4a: definition of subgroups figure 20: interrupt unit microcode enable timing
ma17501 26/35 no. parameter test conditions (1) (2) min (2) typ (2) max (2) units 1 osc - to syncn load 1 10 40 ns 2 osc - to sysclk1n load 1 40 ns 3 osc - to synclkn load 1 40 ns 4 osc - to clkpcn load 1 40 ns 5 osc - to clk02n load 1 40 ns 6 syncn to as - load 1 1 t -10 1 t +5 ns 7 syncn to as (4) load 1 2.5 t -10 2.5 t +15 ns 8 syncn to dsn (read) load 1 3 t -5 3 t +20 ns 9 syncn to dsn (read) (3) load 1 10 30 ns 10 syncn to dsn (write) load 1 3 t -5 3 t +22 ns 11 syncn to dsn - (write) (3) load 1 4.5 t -5 4.5 t +10 ns 12 syncn to address valid load 1 68 ns 13 syncn to data valid load 1 3 t +45 ns 14 syncn to m/ion, rd/wn, in/opn, intren valid load 1 70 ns 15 syncn to hldakn valid load 1 20 ns 16 sysclkn1 to t1 valid load 1 75 ns 17 sysclkn1 to ovin valid load 1 100 ns 18 syncn to ad bus hi-z (read) (6) load 2 3 t +50 ns 19 syncn to ad bus active (read) load 2 15 ns 20 pausen to ad bus hi-z (read) (6) load 2 70 ns 21 pausen - to ad bus valid load 2 60 ns 22 pausen to as, dsn, m/ion, rd/wn, in/iopn hi-z (6) load 2, 3 50 ns 23 pausen - to as, dsn, m/ion, rd/wn, in/iopn valid load 2, 3 59 ns 24 hldakn to ad bus hi-z (read) (6) load 2 60 ns 25 hldakn - to ad bus valid load 2 50 ns 26 hldakn to as, dsn, m/ion, rd/wn, in/iopn hi-z (6) load 2, 3 30 ns 27 hldakn - to as, dsn, m/ion, rd/wn, in/iopn valid load 2, 3 30 ns 28 address after syncn load 1 3 t +15 ns 29 data after syncn load 1 12 ns 30 m/ion, rd/wn, in/opn, intren after syncn load 1 5 ns 31 hldakn after syncn load 1 -7 ns 32 t1n after sysclk1n load 1 15 ns 33 ovin after sysclk1n load 1 20 ns 34 data to syncn 20 ns 35 microcode to clk02n 10 ns 36 microcode to sysclk1n 10 ns 37 rdyn to osc 15 ns 38 irdyn to osc 15 ns 39 data after syncn 0ns 40 microcode after clk02n 5ns 41 microcode after sysclk1n 15 ns 42 rdyn after osc 5ns 43 irdyn after osc 10 ns 44 syncn to syncn (7) 5 t -2 5 t +2 ns 45 reset - to reset (7) 2ns 46 reset - to related outputs valid (7) 50 ns 47 pifn to related outputs valid 50 ns 48 holdn to related outputs valid (7) 50 ns 49 dsn to data valid (write) (7) load 3 (dsn) load 2 (data) 15 ns 50 syncn to synclkn (no.1 - no.3) -5 8 ns 51 clkpcn to synclkn (no.4 - no.3) -5 5 ns 52 sysclk1 to clkpc (no.2 - no.4) -5 10 ns mil-std-883, method 5005, subgroup 9, 10, 11 notes: 1. t a = +25 c, -55 c and +125 c tested at vdd = 4.5v and 5.5v 2. r = 1osc period 0.5r implies 50% osc duty cycle 3. add 1r for internal xlo; nr for memory wait 4. excluding dma and hold conditions 5. unless otherwise noted: v ll = 3 0.0v, v ihttl 4.0v, vihosc = 4.0v timing measured from 50% to 50% points 6. high impedance measured by 20% (of vdd) voltage change using 1k-ohm pullup resistor 7. data obtained by characterisation or analysis, not routinely measured 8. load 2 applies to bus interface signals as, rd/w and in/op; load 3 applies to bus interface signals m/ion and dsn table 4b: timing parameter values
ma17501 27/35 table 5: absolute maximum ratings 6.0 absolute maximum ratings parameter min max units supply voltage -0.5 7 v input voltage -0.3 v dd +0.3 v current through any pin -20 +20 ma operating temperature -55 125 c storage temperature -65 150 c note: stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions, or at any other condition above those indicated in the operations section of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. total dose radiation not exceeding 3x10 5 rad(si) symbol parameter conditions min typ max units v dd supply voltage v ss = 0 4.5 5.0 5.5 v v ihc cmos input high voltage (note 1) - v dd -1 - - v v ilc cmos input low voltage (note 1) - - - v ss +1 v v iht ttl input high voltage (note 2) - 2.0 - - v v ilt ttl input low voltage (note 2) - - - 0.8 v v ch osc input high voltage (note 6) - 4.0 - - v v cl osc input low voltage (note 6) - - - 1.0 v v ohc cmos output high voltage (note 1) i oh = -1.4ma, v dd = 4.5v 4.0 - - v v olc cmos output low voltage (note 1) i ol = 2ma, v dd = 5.5v - - 0.5 v v oht ttl output high voltage (note 2) i oh = -1.4ma, v dd = 4.5v 3.5 - - v v olt ttl output low voltage (note 2) i oh = -1.4ma, v dd = 4.5v - - 0.4 v v ohclk clock output high voltage (note 3) i oh = -12ma, v dd = 4.5v 4.0 - - v v olclk clock output low voltage (note 3) i ol = 12ma, v dd = 5.5v - - 0.5 v i i input leakage current (note 4) v dd = 5.5v, v in = 0v or 5.5v - - 10 m a i oz output leakage current (note 4) v dd = 5.5v, v o = 0v or 5.5v - - 50 m a i ipu testn input pullup current (note 5) v dd = 5.5v, testn = 0v - -150 -300 m a i ddop operating supply current v dd = 5.5v, osc = 20mhz - 25 35 ma i ddst static supply current v dd = 5.5v, osc = 0mhz - 5 10 ma mil-std-883, method 5005, subgroup 1, 2, 3. notes: 1. the following signals are cmos compatible: a) cmos inputs: microcode bus, (m00-m19), testn, irdyn and pifn. b) cmos outputs: t1, ovin, intren, sysclk1n, clkpcn and clk02n. 2. the following signals are ttl compatible: a) ttl inputs: holdn, reset, pausen, rdyn and osc. b) ttl outputs: holdakn and syncn. c) ttl 3 state outputs: as, dsn, m/ion, rd/wn and in/opn. d) ttl 3 state i/o signals: address/data bus (ad00-ad15). 3. the clock output pins, sysclk1n, synclk, clkpcn and clk02n have a higher drive capability than the standard outputs. 4. worst case at t a = +125 c, guaranteed but not tested at t a = -55 c. 5. the testn input signal is used during chip test and has an integral pullup reistor. in normal operation testn is at v dd . 6. guaranteed but not tested. 7.0 dc electrical characteristics table 6: operating dc electrical characteristics
ma17501 28/35 8.0 packaging information ref millimetres inches min. nom. max. min. nom. max. a - - 5.715 - - 0.225 a1 0.38 - 1.53 0.015 - 0.060 b 0.35 - 0.508 0.014 - 0.020 c 0.229 - 0.36 0.009 - 0.014 d - - 82.04 - - 3.230 e - 2.54 typ. - - 0.100 typ. - e1 - 22.86 typ. - - 0.900 typ. - h 4.71 - 5.38 0.185 - 0.212 me - - 23.4 - - 0.920 z - - 1.27 - - 0.050 w - - 1.53 - - 0.060 xg413 figure 21a: 64-lead ceramic dil - package style c d w a e b z h a 1 15 m e c e 1 seating plane
ma17501 29/35 figure 21b: pin assignments 1 osc 2 nc 3 synclk1n 4 synclkn 5 clkpcn 6 clk02n 7 as 8 dsn 9 gnd 10 m/ion top view 11 rd/wn 12 gnd 13 in/opn 14 intren 15 pifn 16 m19 17 m18 18 m17 19 m16 20 m15 21 m14 22 m13 23 m12 24 m11 25 m10 26 m09 27 m08 28 m07 29 m06 30 m05 31 m04 32 m03 64 syncn 63 rdyn 62 irdyn 61 ovin 60 t1 59 pausen 58 hldakn 57 reset 56 holdn 55 ad00 54 ad01 53 ad02 52 gnd 51 ad03 50 ad04 49 ad05 48 ad06 47 ad07 46 ad08 45 ad09 44 ad10 43 ad11 42 vdd 41 nc 40 ad12 39 ad13 38 ad14 37 ad15 36 testn 35 m00 34 m01 33 m02
ma17501 30/35 ref millimetres inches min. nom. max. min. nom. max. a 1.905 - 2.21 0.075 - 0.087 b1 - 0.51 - - 0.020 - d 18.08 - 18.62 0.712 - 0.733 e 18.08 - 18.62 0.712 - 0.733 e - 1.02 - - 0.040 - z 1.40 - 1.78 0.055 - 0.070 xg493 bottom view pad 1 radius r 3 corners e z e b 1 d a figure 22a: 64-lead leadless chip carrier - package style l
ma17501 31/35 figure 22b: pin assignments bottom view 6 5 4 3 2 1 64 63 62 61 60 59 25 26 27 28 29 30 31 32 33 34 35 36 m10 m09 m08 m07 m06 m05 m04 m03 m02 m01 m00 testn clk02n clkpcn synclkn sysclk1n nc osc syncn rdyn irdyn ovin t1 pausen 20 19 18 17 16 15 14 13 12 11 10 9 gnd m/ion rd/wn gnd in/opn intren pifn m19 m18 m17 m16 m15 41 42 43 44 45 46 47 48 49 50 51 52 gnd ad03 ad04 ad05 ad06 ad07 ad08 ad09 ad10 ad11 vdd nc 8 7 dsn as 24 23 22 21 m14 m13 m12 m11 37 38 39 40 ad15 ad14 ad13 ad12 53 54 55 56 holdn ad00 ad01 ad02 58 57 hldakn reset
ma17501 32/35 ref millimetres inches min. nom. max. min. nom. max. a - - 2.72 - - 0.107 a1 1.83 - 2.24 0.072 - 0.088 b 0.41 - 0.51 0.016 - 0.020 c 0.20 - 0.30 0.008 - 0.012 d1, d2 23.88 - 24.51 0.940 - 0.960 e - 2.54 - - 0.050 - j1 - 1.02 - - 0.040 - j2 - 0.51 - - 0.020 - l 10.16 - 10.54 0.400 - 0.415 z 1.65 - 2.16 0.065 - 0.085 xg540 figure 23a: 68-lead topbraze flatpack - package style f top view j1 d1 l pin 1 j2 b e d2 z a1 a c
ma17501 33/35 figure 23b: pin assignments top view 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 dsn as clk02n clkpcn synclkn sysclk1n nc nc osc syncn rdyn irdyn ovin t1 pausen hldakn reset m11 m10 m09 m08 m07 m06 m05 m04 m03 m02 m01 m00 testn ad15 ad14 ad13 ad12 m12 m13 m14 m15 m16 m17 m18 m19 pifn intren in/opn nc gnd rd/wn m/ion gnd nc nc nc vdd ad11 ad10 ad09 ad08 ad07 ad06 ad05 ad04 ad03 gnd ad02 ad01 ad00 holdn
ma17501 34/35 9.0 radiation tolerance total dose radiation testing for product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. the sample devices will be subjected to the total dose radiation level (cobalt-60 source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. electrical tests, pre and post irradiation, will be read and recorded. dynex semiconductor can provide radiation testing compliant with mil-std-883 method 1019 ionizing radiation (total dose) test. total dose (function to specification)* 3x10 5 rad(si) transient upset (stored data loss) 1x10 11 rad(si)/sec transient upset (survivability) >1x10 12 rad(si)/sec neutron hardness (function to specification) >1x10 15 n/cm 2 single event upset** <1x10 -10 errors/bit day latch up not possible * other total dose radiation levels available on request ** worst case galactic cosmic ray upset - interplanetary/high altitude orbit table 10: radiation hardness parameters 10.0 ordering information for details of reliability, qa/qc, test and assembly options, see manufacturing capability and quality assurance standards section 9. unique circuit designator s r q radiation hard processing 100 krads (si) guaranteed 300 krads (si) guaranteed radiation tolerance c f l ceramic dil (solder seal) flatpack (solder seal) leadless chip carrier package type qa/qci process (see section 9 part 4) test process (see section 9 part 3) assembly process (see section 9 part 2) l c d e b s rel 0 rel 1 rel 2 rel 3/4/5/stack class b class s reliability level max17501xxxxx
ma17501 35/35 customer service centres france, benelux, italy and spain tel: +33 (0)1 69 18 90 00. fax: +33 (0)1 64 46 54 50 north america tel: 011-800-5554-5554. fax: 011-800-5444-5444 uk, germany, scandinavia & rest of world tel: +44 (0)1522 500500. fax: +44 (0)1522 500020 sales offices france, benelux, italy and spain tel: +33 (0)1 69 18 90 00. fax: +33 (0)1 64 46 54 50 germany tel: 07351 827723 north america tel: (613) 723-7035. fax: (613) 723-1518. toll free: 1.888.33.dynex (39639) / tel: (831) 440-1988. fax: (831) 440-1989 / tel: (949) 733-3005. fax: (949) 733-2986. uk, germany, scandinavia & rest of world tel: +44 (0)1522 500500. fax: +44 (0)1522 500020 these offices are supported by representatives and distributors in many countries world-wide. ? dynex semiconductor 2000 publication no. ds3564-5 issue no. 5.0 january 2000 technical documentation C not for resale. printed in united kingdom headquarters operations dynex semiconductor ltd doddington road, lincoln. lincolnshire. ln6 3lf. united kingdom. tel: 00-44-(0)1522-500500 fax: 00-44-(0)1522-500550 dynex power inc. unit 7 - 58 antares drive, nepean, ontario, canada k2e 7w6. tel: 613.723.7035 fax: 613.723.1518 toll free: 1.888.33.dynex (39639) this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is made regard ing the capability, performance or suitability of any product or service. the company reserves the right to alter without prior notice the specification, design or price of any product or service. information con cerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user's responsibility to f ully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to the company's conditions of sale, w hich are available on request. all brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respec tive owners. http://www.dynexsemi.com e-mail: power_solutions@dynexsemi.com datasheet annotations: dynex semiconductor annotate datasheets in the top right hard corner of the front page, to indicate product status. the annota tions are as follows:- target information: this is the most tentative form of information and represents a very preliminary specification. no actual design work on the product has been started. preliminary information: the product is in design and development. the datasheet represents the product as it is understood but details may change. advance information: the product design is complete and final characterisation for volume production is well in hand.

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